Our paper, titled “Compressing Analog Tests One-at-a-time to Lower Production Costs”, was accepted to the 21st Asia and South Pacific Design Automation Conference (ASP-DAC 2016). This was a work in collaboration with Suriyaprakash Natarajan from Intel.

Here is the abstract of the paper:
Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functionals of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by 93%.